发明名称 CONTROLLER WITH PRIORITY
摘要 PURPOSE:To reduce the time required for the determination of priority, by providing the priority determining circuit which determines the priority of right using common resouce with each device with scattering. CONSTITUTION:Data processing units (PU) 1301-13064 use a common memory unit, not shown, in time-sharing. PUs 1301-13064 produce request signals REQ1- REQ64 when the common memory device is desired to be used and receive acknowledgement signals ACK1-ACK64. Priority determining circuits (unit) 1401-14064 are provided corresponding to PUs 1301-13064 to supply REQ1-REQ64. Synchronizing signal SYNC is fed from the synchronizing signal generator 150 to the units 1401-14064. Since the ACK signal is output to the units 1401-14064 according to the REQ signal distributed on the binary interrupting line 160 connected to the discrimination line, the time required for judgement can be reduced.
申请公布号 JPS56118151(A) 申请公布日期 1981.09.17
申请号 JP19800020522 申请日期 1980.02.22
申请人 TOKYO SHIBAURA ELECTRIC CO;KUMADA ICHIROU;AIISO HIDEO 发明人 AIISO HIDEO;KUMADA ICHIROU;YAMAZAKI ISAMU;SATOU TAI
分类号 G06F9/46;G06F9/52;G06F12/00;G06F13/18;G06F13/368;G06F15/16;G06F15/177 主分类号 G06F9/46
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