发明名称 ACL SIGNAL GENERATING CIRCUIT IN INTEGRATED CIRCUIT
摘要 PURPOSE:To enable to give stable initial state to an integrated circuit, by providing circuit with desired number of stages to which the output of oscillation circuit is given, and a logic circuit to form ACL signal through the detection of the level of this frequency-division output. CONSTITUTION:When the power supply -V is given, a node 8 is gradually charged from GND level to -V level, and the information is given to a node 5 via inverters 9, 10, but when the level of the node 5 is at GND level, a frequency division circuit 3 is reset, MOS11 of a logic circuit 4 is on, MOS12 is off, and the ACL signal introduced from the circuit 4 is at GND level. When the oscillation of a crystal oscillation circuit 1 is started for a given time, a frequency divider output signal f1 is inverted to -V level, MOS11 is off and MOSs 12, 13 are on, the latch circuit consisting of MOSs 14-17 of the circuit 4 is inverted, ACL signal of -V level is outputted to the integrated circuit to complete the power on clear operation. Since the capacitance 7 charging the node 8 uses integrated circuits, the ACL signal generating circuit suitable for circuit integration can be obtained.
申请公布号 JPS56116323(A) 申请公布日期 1981.09.12
申请号 JP19800019524 申请日期 1980.02.18
申请人 SHARP KK 发明人 NISHIURA YOSHIKAZU;MINEYAMA TAKIJI;INOUE KAZUO
分类号 H03K21/38;H03K3/356;H03K17/22 主分类号 H03K21/38
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