| 摘要 |
PURPOSE:To obtain an address signal for both the multiplication and the multiplex isolation of the data having optional types of speeds, by storing previously the address signal corresponding to the type of speed of the data in the synchronous data transmission system. CONSTITUTION:The clock CLK is counted by the counters CTR1 and CTR2 each, and the address signals AD3 and AD4 are read out of the ROM1-ROM3 by the count output plus the data speed setting signals S1-S3. At the same time, the address signals AD0-AD2 are obtained from the output of the counter CTR1. Based on these address signals, both the multiplication and the multiple isolation are possible for the data having different speeds. |
