| 摘要 |
<p>Circuitry for automatically and selectively refreshing a dynamic node to a desired logic level. Nodes at ground potential are left at ground while nodes at an intermediate level are brought up to a supply voltage level. In a preferred use the dynamic node is a digit line in a random access memory. The circuitry includes a first transistor (26) connected between the drain supply and a digit line (12) having a gate (28) connected to the source of a second transistor (30). The drain of the second transistor (30) is connected to a clocked source of potential at least one threshold above the drain supply. The gate (32) of the second transistor (30) is precharged to a potential near the drain supply voltage preferably concurrent with precharging of digit lines in the memory proper. A third transistor (34) is connected between the gate (32) of the second transistor (30) and the digit line (12) and has a gate (36) connected to a clocked source of a reference potential between a digit line precharge level and the level of one threshold above ground. After the state of a memory cell (16) is read out by a sense amplifier (20), the reference potential is applied to the gate (36) of the third transistor (34) to discharge the gate of the second transistor (30) in the event that the digit line (12) is at a low voltage. If the cell read out on the digit line (12) was at a high potential the gate (32) of the second transistor (30) remains charged so that when a potential exceeding the drain voltage by at least one threshold is applied to the drain of the second transistor (30) it is coupled through to the gate (28) of the first transistor (26) which in turn pulls the digit line potential to the drain supply voltage. </p> |
