| 摘要 |
<p>A method is disclosed for selectively modifying the electrical characteristics of MOS devices at a late stage in the fabrication process to form, for example, the "1" and "0" data locations of a ROM, or to form enhancement-and depletion-mode devices. In one embodiment of the method, in addition to forming openings in the passivation layer to define location of bonding pads, additional openings are formed in that layer at locations at which a data bit of one of the two levels is to be formed. Subsequently, an ion implantation is performed through the exposed underlying polysilicon gate structure to create an implantation layer at the channel regions of selected MOS devices, and thereby permanently alter the threshold voltages of these MOS devices. Other embodiments of the invention are disclosed in which ion implantation is performed through openings selectively formed in other layers, thereby to form implantation regions at selected locations to modify selected MOS devices at those locations.</p> |
