发明名称 RECEPTION SYSTEM OF PRIORITY CHANNEL
摘要 PURPOSE:To enable the reception with one set of tuner, by alternately receiving priority channel and arbitrary channel and monitoring the priority channel in a short time for a given time interval, when the priority channel is first received. CONSTITUTION:A code selection circuit 1 outputs a two signal codes so that the priority channel and arbitrary channel can alternately be received in the duty cycle of 50% when the priority channel code is not input. Further, when an arbitrary channel is received, since the circuit 1 outputs a signal of low level to the terminal 1', a high level signal is input to one input terminal of an NAND circuit 12. Further, since the squeltch signal is at high level, the signal of low level is input to the terminal 8' of the counter circuit 8, the output of the circuit 8 is changed to change the duty cycle of the circuit 1, and the code is output so that the priority channel is received in a short time for a given time interval. With this state, when the signal in the priority channel is received, the oscillation of a pulse oscillator 9 is stopped and the channel is fixed to the priority channel.
申请公布号 JPS5696535(A) 申请公布日期 1981.08.04
申请号 JP19790173100 申请日期 1979.12.29
申请人 GEN RES ELECTRONICS INC 发明人 IMAZEKI KAZUYOSHI;TANAKA TOSHIYUKI
分类号 H03J7/00;H03J7/18;H04B1/16 主分类号 H03J7/00
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