| 摘要 |
PURPOSE:To make easy circuit integration, to remove broad noise, to prevent malfunction and to increase the accuracy, by detecting the level of synthesized synchronizing signal at window period and obtaining the output without level change. CONSTITUTION:To an input terminal 63, synthesized synchronizing signal SYNC including signals such as horizontal synchronizing signal HD, equalizing pulses EQ, EQ', and vertical synchronizing signal VD0 is fed, and a vertical synchronizing signal VD is obtained at an output terminal 64 and it is output as the pulse indicating a given location of the period of the synchronizing signal VD0. From the position where the signal SYNC is at low level, the window signal to detect the vertical signal and noise is made. Whether or not the SYNC is at high level during the window period is detected, and the period, for example, 4 consecutive period, are regarded as the signal VD0. Thus, circuit integration is made easy, the malfunction against broad noise is avoided and the accuracy can be increased. |
