| 摘要 |
PURPOSE:To ensure the distinction of data from control signal at demodulation and to simplify the circuit constitution, by making different the signal inversion interval based on the frame synchronizing signal from that based on data. CONSTITUTION:Data DA1 in NRZ is fed to a terminal T1, readout clock CK1 of DA1 is to the terminal T2 and CK2 frequency dividing CK1 is fed to the terminal T3. CK1 and CK2 are fed to the circuit 10 to form CK3, CK4 having the same period and shifted by semiperiod for the phase. Further, DA1 is fed to D-FF11, it is latched with CK4, and the signal inverting 12 the output Q and the signal CK3 inverting 13 DA1 are fed to an AND gate 14, and CK3 is output from the gate 14 when DA1 is at 0 level continuously two periods or more for CK1. Further, CK4 is output from the gate 15 when DA1 is at 1 level. Thus, the clock output from an OR gate 16 is frequency-divided at FF17 to obtain the self clocking information in MFM modulation from the output Q. |
