| 摘要 |
PURPOSE:To obtain a high-speed and low-power consumption complementary signal logic circuit, by securing a combination between the two units of depletion-type MIS transistors connected in parallel and two enhancement-type MIS transistors connected in series. CONSTITUTION:The transistors 1, 2, 5 and 6 are the depletion-type MIS transistors approximate to the enhancement type; and the transistors 3, 7, 4 and 8 are the enhancement-type MIS transistors. The transistors 1/2 and 7/8 form the parallel transistor pairs TP1 and TP2 respectively; and the transistors 3/4 and 5/6 form the serial transistor pairs TS1 and TS2 each. Then various types of logic signals are obtained as shown in the table from the output terminals C1 and C2 by the signals to be applied to the input terminals A1, A2, B1 and B2 each. |
