Semiconductor memory circuit.

摘要

The memory circuit has a right memory cell group MR and a left memory cell group ML between which word decoders (WDk) are located. Each word decoder is provided with left and right memory cell group selection and drive gates 31L and 31R. One or other of gates 31L and 31R is closed in dependence upon a discrimination output provided from discrimination means which indicate to which memory cell group (ML or MR) a memory cell to be accessed belongs.