发明名称 |
Phase-locked loop speed control system using programmable counter for frequency pulling |
摘要 |
A phase-locked loop system for controlling the speed of a motor or the like comprises an oscillator generating clock pulses or the like comprises a programmable frequency divider receptive of clock pulses for delivery of output pulses at a frequency which is an integral submultiple of the clock frequency, the integral submultiple being variable as a function of external supplied digital signals. A phase comparator compares speed related pulses. A transducer generates pulses at a repetition frequency related to the speed of the motor which is compared in the phase comparator with the output pulse from the frequency divider for driving the motor. A programmable binary counter is provided which is reset in response to the beginning of each period of the speed related pulses for counting the clock pulse. A logic gate circuit is connected to the counter stages of the programmable counter to define a range of pulse counts to generate motor control voltage signals when the count falls outside of the defined range.
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申请公布号 |
US4278925(A) |
申请公布日期 |
1981.07.14 |
申请号 |
US19790044149 |
申请日期 |
1979.05.31 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL COMPANY |
发明人 |
MINAKUCHI, HIROSHI |
分类号 |
G05D13/62;H02P23/00;(IPC1-7):H02P5/16 |
主分类号 |
G05D13/62 |
代理机构 |
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