发明名称 COMPLEMENTARY MOS TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To avoid the decrease of a negative resistance breakdown voltage due to a parasitic transistor without increasing the pattern area by forming a channel stopper region forming a C-MOSFET in contact with a source region when forming the C- MOSFET. CONSTITUTION:The configuration of the FET forming the C-MOSFET is formed as follows: A p type well region 40 is diffused in an n type Si substrate 39, an n<+> type source region 42 and an n<+> type drain region 41 are formed therein, and are surrounded by a P<+> type channel stopper region 43 formed between the end of the region 40 and the substrate 39. In this configuration, the stopper region 43 of the source region 42 side is formed in contact with the region 42, and the regions 42 and 43 are commonly connected using a Vss wire 46. Thus, the effect of the parasitic transistor 51 within the region 40 caused by the region 42 and the substrate 39 is reduced, thereby preventing the decrease of the negative resistance breakdown voltage and enabling the operation with high power source voltage.
申请公布号 JPS5685851(A) 申请公布日期 1981.07.13
申请号 JP19790162840 申请日期 1979.12.17
申请人 OKI ELECTRIC IND CO LTD 发明人 INOUE HIROSHI;NAKAMURA TSUNEO
分类号 H01L27/08;H01L27/092;H01L29/78 主分类号 H01L27/08
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