| 摘要 |
PURPOSE:To prevent out of a vertical synchronism, by inhibiting the application of a reset pulse every synchronizing signal vertically to a 1/525 frequency division circuit to obtain a vertical scanning signal, if the horizontal synchronism is lost. CONSTITUTION:Two times the horizontal oscillation pulse is produced at the horizontal circuit 9. On the other hand, the vertical signal in 60Hz is obtained by frequency dividing the double horizontal oscillation pulse at the 1/525 frequency division circuit 11. Further, in the horizontal AFC voltage, spike voltage is produced evey vertical blanking period, and if the horizontal synchronism is lost, the amplified output with transistors TRs 15, 16 is out of the comparison range of the comparators 17, 19. Thus, the output of the counter consisting of FF21-23 and FF25-27 is a given value or more, and the output of NAND gates 24, 28 is at L level signal within the same vertical scanning period. Thus, the output of the NAND gate 37 is at L level and the AND gate 38 is closed. Thus, the reset pulse is not fed to the circuit 11 and the vertical scanning is not stopped. |
