| 摘要 |
PURPOSE:To enable high-speed data processing by shortening memory cycles easily without using a high-speed memory element when repeatedly returning the arithmetic result of data read out of a memory unit. CONSTITUTION:Arithmetic between the output of multiplexer 24 and an operand is performed by operator 25, data to be written in memory units 211 and 212 are held in write registers 261 and 262, and addresses for memory units 211 and 212 are set in address counter 22 in common. Then, counter 22 is made to count up one by one successively and respective arithmetic results of contents of addresses A, A+1, A+2,... of memory units 211 and 212 are written in not the same addresses in memory units 211 and 212 but addresses preceding by one. When every address is assigned once, counter 22 is made to count down under the control of the arithmetic unit and this operation is repeated, so that the data can be processed at a high speed. |
