| 摘要 |
<p>A data recovery circuit (20) for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal (ENDATA). The data recovery circuit (20) includes a time delay circuit for delaying the PE pulse signal (ENDATA) by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal (CNTRL) that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal (ENDATA). The control signal (CNTRL) is used to generate a recovered clock signal (RCLK) by logically combining the control signal (CNTRL) with the PE pulse signal (ENDATA) and a one-half bit period delayed PE pulse signal (HBTD). The control signal (CNTRL) is also used to generate a recovered data signal (RDATA) by clocking the control signal (CNTRL) into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops. </p> |
