发明名称 |
Interruption control method for multiprocessor system |
摘要 |
An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.
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申请公布号 |
US4268904(A) |
申请公布日期 |
1981.05.19 |
申请号 |
US19780969008 |
申请日期 |
1978.12.13 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO., LTD. |
发明人 |
SUZUKI, SEIGO;EGUCHI, SEIJI |
分类号 |
G06F9/48;(IPC1-7):G06F9/46;G06F15/16 |
主分类号 |
G06F9/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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