| 摘要 |
<p>The switching matrix with a plurality of individual lateral type PNPN type switching elements is disposed on a one chip silicon. the chip includes a double layered substrate having a thin P type layer with low impurity concentration epitaxial-grown on a P+ type layer with high impurity concentration and an N type layer. The substrate has a low resistance. An N+ type buried layer with high impurity concentration is diffused into the junction between the P type layer and the N type layer at the location where the switching element is to be disposed. The switching element is formed in the N type layer right above the N+ type buried layer. P+ type isolation region with high impurity concentration is diffused into the N type layer, not contacting the N+ type buried layer but the substrate P type layer and enclosing the N type gate region of the switching element. At this time, between adjacent region of the N type layer. With such a construction, the low resistive P/P+ type double layered substrate and the high resistive N separation layer cooperate to remarkably reduce the signal crosstalk between switching elements.</p> |
