发明名称 ANALOG SIGNAL DELAY CIRCUIT
摘要 PURPOSE:Not only to omit a multiplexer and reduce the number of parts but also to simplify the control, by providing RAM between the sequential approximate register and the D/A converter. CONSTITUTION:When a start command 11 is provided to the sequential approximate register 3, RAM8 becomes a writing mode by a control signal 12, and RAM8 becomes a state that the input and the output are short-circuited in its inside. And the regular A/D conversion is executed by the comparator 1, the sequential approximate register 3 and the D/A converter 2, and its digital value is written in the address designated by the counter 9 of RAM8, by the control signal 12. When the contents of RAM8 are read out by the counter 9 after a prescribed time has passed, a delayed analog signal is received by the terminal 6 through the D/A converter 2 and the simple holding circuit 7.
申请公布号 JPS5652923(A) 申请公布日期 1981.05.12
申请号 JP19790129626 申请日期 1979.10.08
申请人 WATANABE INSTR 发明人 OOTA KENICHIROU
分类号 H03M1/00;H03H11/26;H03H17/08 主分类号 H03M1/00
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