发明名称 |
Logarithmic digital step signal generator - uses cascaded memories addressed by calculator from live memory |
摘要 |
<p>Cascaded memories each provide a continuous series of logarithmic steps permitting variation of the level of digital signals, allowing attenuation characteristics to be measured in a repetitive and reproductive manner for digital filters. A number of dead memories (4-7) are connected in cascade and are addressed by a live memory (8). The live memory is controlled by a calculator or may be controlled manually to address the respective memories to obtain the required logarithmic steps. Thus the signals at the input (1) are attenuated and obtained from the output (3). One of the memories may be used to provide amplification, with the other memories, providing intermediate and attenuation values.</p> |
申请公布号 |
FR2468917(A1) |
申请公布日期 |
1981.05.08 |
申请号 |
FR19790021768 |
申请日期 |
1979.08.30 |
申请人 |
MATERIEL TELEPHONIQ THOMSON CSF |
发明人 |
JEAN-PIERRE LE PABIC ET JEAN-CLAUDE LEDEY |
分类号 |
G01R27/28;G06F1/035;(IPC1-7):01R29/02;03H17/00 |
主分类号 |
G01R27/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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