| 摘要 |
A CMOS device comprising an N type semiconductor substrate, a P type well region diffused in the substrate, an n-channel MOS transistor formed in the P type well region, and a p-channel MOS transistor formed in the N type semiconductor substrate, and a method for manufacturing the CMOS device. In case the CMOS device serves as a CMOS inverter, the source region of the p-channel MOS transistor, the semiconductor substrate and the well layer constitute a parasitic PNP type bipolar transistor, and the source region of the n-channel MOS transistor, the well layer and the semiconductor substrate constitute a parasitic NPN type bipolar transistor. The product of the current amplification factor beta 1 of the PNP type bipolar transistor and the current amplification factor beta 2 of the NPN type bipolar transistor is smaller than 1. |
| 申请人 |
TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA, JP |
发明人 |
SATOU, KAZUO, YOKOHAMA, KANAGAWA, JP;UENO, MITSUHIKO, FUJISAWA, KANAGAWA, JP |
