| 摘要 |
A high sensitivity voltage comparator circuit, suitable for integration in monolithic form is disclosed. First and second p-channel field effect transistors, FETs, are arranged as a first cascode amplifier between a relatively positive supply potential and an output node. First and second n-channel FETs are arranged as a second cascode amplifier similar to the first which is connected between a source of relatively negative supply potential and the same output node. Bias potentials are selectively applied to each of the gate electrodes of the FETs to balance the composite amplifier concurrently with application of a reference signal via input coupling capacitor, to the amplifier inputs. Subsequently signal potential is selectively applied to the amplifier inputs, to the exclusion of the reference potential.
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