| 摘要 |
PURPOSE:To make it possible to detect even a differential input of a level lower an input offset characteristic to a differential amplifier by a new signal input system. CONSTITUTION:When clock signal phi2 rises up to +5V at time t1, transistors 3-6 turn on to equalize potentials VA, VG, VB and VD at points A, G, B and D, electrodes of capacitors C1 and C2, to V-IN, VR, VIN, AND VR'. Then when clock signal phi1 rises up to +5V at time t3, transistors 1 and 2 conduct to equalize VA and VB to VIN and V-IN respectively. Therefore, as VA changes from V-IN to VIN at time t3, VG also changes from VR to VR+(VIN-V-IN). Similarly, when VB changes from VIN to V-IN at time t3, VD also changes from VR' to VR'+ (V-IN-VIN). If VR=VR', differential voltage VGD between input voltages VG and VD of differential amplifier S.A is ¦VIN-V-IN¦X2 at time t eventually, which is twice as much as the differential voltage of the original input signal. |
