| 摘要 |
PURPOSE:To enable the efficient access to the memory slow in the access time, by supplying the row address and strobe signal to the memory after the output of status signal and supplying the column address and strobe signal after that. CONSTITUTION:The processor 1 produces the signal ST indicating the write-in/ readout status at the access to the memory 3, after the confirmation of the addresses A0-A7, and generates the write-in/readout strobe pulses RD, WR after that. In this case, the addresses A0-A7 are divided into two, row and column addresses, with the multiplexer 2, and the row address is given to the address inputs A0'- A3' of the memory 3, and when the signal ST is fed to the memory 3, the row address is confirmed. After that, the signal delaying 4 the signal ST is given to the circuit 2 to supply the column address to the memory 3, and when the pulses WD, RD are output, pulse R/W and CAS signal are given to the memory 3 to enable write-in/readout of information is made. |
