| 摘要 |
A universal register which consists of a plurality of identical emitter coupled logic (ECL) bit slices and auxiliary ECL gates adapted for fabrication on a single large scale integration (LSI) chip. Each bit slice is comprised of a master-slave flip-flop (a master latch circuit and a slave latch circuit) and an output control network which is driven by the flip-flop. Each of the latch circuits and the output control network comprises a single stage (unit propagation delay), two decision level cascode ECL circuit. The output control network selectively supplies either the Q or the Q output signal from the flip-flop or a logic zero signal to the network's output terminal (designated P). The control network responds to applied select (S) and enable (E) signals so that when the S signal is at a high level (logic 1) and the E signal is at a low level (logic zero) the Q signal is fed to the P output terminal; when the E and S signals are both at a low level, the Q signal is fed to the P output terminal; and when the E signal is at a high level the signal at the P output terminal is held at the low (logic zero) level. This just described enable feature of the invention allows for "wire-OR" connection of the P output terminal from a given ECL circuit to the output terminals of other ECL circuits so as to facilitate the implementation of a variety of processor circuits, such as, for example, toggle/hold circuits, expandable counters, J-K flip-flops and shift registers.
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