| 摘要 |
PURPOSE:To shorten readout time by making even the load capacity of a digit line by providing a switch circuit that determines whether the output of ROM should be sent out in phase or out of phase. CONSTITUTION:Denoting as 0 and 1 data that corresponds to whether memory cell Tr exists or not, the number of cells Tr loaded on digit lines DL0-DL3 increases as there are many data 0. Now, when the number of address input lines A0-A3 is denoted as N, values out of phase with lines DL0-DL3 are output to data output terminals D0-D3 by switch circuit P only as to lines DL0-DL3 where the number of cell Trs added to line DL0-DL3 exceeds N/2. With regard to the relation between cell Trs and data, lines DL0-DL3 are held at ''1'' when there are cell Trs and at ''0'' when not. Consequently, data agree in logic can the load capacity of the digit lines is reduced. |
