| 摘要 |
This invention relates to a memory control circuit having a plurality of address groups and a plurality of bit groups running in rows and columns to form a matrix, and a plurality of memory cells (30 min , 32 min ...40 min ) disposed at the intersection of the matrix. With a view to providing such a circuit in which two or more memory cells may be selected simutaneously for writing and reading purposes, each cell is connected to a plurality of address lines (10a, 10 min a) and a plurality of bit lines (20c, 20 min c). A first peripheral control unit (50) selects the first address and bit lines in response to a first control signal and a second peripheral control unit (50 min ) selects the second address and bit lines in response to a second control signal.
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