发明名称 Dual redundant error detection system for counters
摘要 A pair of identical multiple stage digital counters receive count advance inputs designating the occurrence of the event being monitored but with the inputs displaced so the counters do not advance simultaneously. Only the upper order stages of the counters are compared so the contents will appear equal at times and different at other times. If the compared counts are different when they should be equal or equal when they should differ, an error is indicated.
申请公布号 US4255809(A) 申请公布日期 1981.03.10
申请号 US19790090555 申请日期 1979.11.02
申请人 HILLMAN, DALE A. 发明人 HILLMAN, DALE A.
分类号 G06F11/16;(IPC1-7):G06F11/16;H03K21/34 主分类号 G06F11/16
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