| 摘要 |
PURPOSE:To shorten the required time by composing again so as to operate the circuit element which is operating serially in parallel and retaining the required time necessary for one cycle of the operation under minimum time unit. CONSTITUTION:In the basic cycle of the divider, the result of the addition and subtraction by ADD/SUB (processing of adder) is not decoded but upper rank 4 bits and DIVISOR upper rank 2 bits of PARTIAL REMAINDER (partial multiplication and division) and SUBSTRACTER (+ or -n times DIVISOR) are directly decoded. In this manner, the decode in DECODE can be started at the time of the same point as the starting point of the addition and subtraction by ADD/SUB and completed at the time of further before the completion point of the addition and subtraction. The correction of the decode is done in SELECT by waiting the carry signal from ADD/SUB and this correction can be completed before the final output time of ADD/SUB. |
