发明名称 CONTROL CLOCK SWITCHING SYSTEM
摘要 PURPOSE:To detect previously degradation of functions of various logical elements of a data processing unit, by selecting plural control clocks from the generating means, which generates control clocks, by a selecting means and by controlling this selecting means by microinstructions. CONSTITUTION:Plural kinds of control clock CL0-CLn generated by a clock generating means are transferred to clock switching circuit 6, and one of clocks CL0-CLn is selected by circuit 6 and is output according to the control signal transferred from decoder 5. Information stored at the address of memory 2 is held in data register 3 by indication of data held in address register 1, and further, information held in register 3 is held in instruction register 4, and the instruction in information of register 4 is decoded by decoder 5. In case that this instruction is the switching instruction for control clocks, the switching control signal is transferred from decoder 5 to circuit 6, and one of clocks CL0-CLn is selected and output, so that functions of various logical elements of the data proccessing unit can be checked.
申请公布号 JPS5614353(A) 申请公布日期 1981.02.12
申请号 JP19790088566 申请日期 1979.07.12
申请人 FUJITSU LTD 发明人 MAEDA TAKESHI
分类号 G06F9/22;G06F1/04;G06F11/22 主分类号 G06F9/22
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