发明名称 SETTING CIRCUIT FOR DATA LINE POTENTIAL
摘要 PURPOSE:To make it possible to obtain rapidly a difference in level in the 2nd potential state by discharging the capacity of one common data line to that of the other line by way of a switching method connected between the common data lines. CONSTITUTION:Once write recovery signal phiWR1 is applied to MISMFTQ11 of switching method 9', capacitance C0 is discharged via FETQ11, so that while common data line CD0 increases in level, CD1 falls in level. Since FETQ11 is operating within the unsaturable range of output current, its operation resistance is extremely small and lines CD0 and CD1 change from the 1st potential state nearly to the 2nd potential state at a high speed. Next, when address signal Ai for address decoders 2 and 4 is switched and the memory cell is changed from MS11 over to MSmn selectively, the potentials of lines VD0 and CD1 are inverted since cross-connection points A' and B' of cell MSmn are held at the reverse potentials of lines DC0 and CD1. Consequently, level corrections by cell MSmn can be made rapidly.
申请公布号 JPS5613584(A) 申请公布日期 1981.02.09
申请号 JP19790086927 申请日期 1979.07.11
申请人 HITACHI LTD 发明人 NOGUCHI YOSHIO
分类号 G11C11/409;G11C11/41;G11C11/412;G11C11/417;G11C11/419 主分类号 G11C11/409
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