| 摘要 |
1534053 Rejecting spurious pulses UNITED TECHNOLOGIES CORP 1 March 1976 [3 March 1975] 08092/76 Heading H3T Changes lasting more than a preset time from either level of a two level logic signal to the other are detected by sensing the occurrence of a transition in said signal, actuating timing means having a preset timing period upon the occurrence of a transition from a first level to a second level, resetting the timing means if the logic signal returns to the first level before the end of the preset period and producing a first output signal at the end of the period if the timing means is not reset. Once the first output signal has been produced, a transition to the first level reactuates the timing means, which is reset if a transition to the second level occurs before the end of the preset period and a second output signal is produced upon expiration of the period if the timing means is not reset. Two embodiments using TTL circuits are described. In one embodiment, Fig. 3 (not shown) three flipflops are used with a synchronous counter as timing means in a circuit which gives a short pulse out on one of two lines each time the input makes a valid high or low transition. In the other embodiment, Fig. 4 (not shown) a monostable circuit is used as timing means together with two flip-flops in a circuit which gives a continuous high or low signal according as the input is high or low. |
