| 摘要 |
In highspeed digital communication systems a number of tributary data streams may be multiplexed into a single main data stream having a higher aggregate data rate. This main data stream contains frame alignment information to achieve correct demultiplexing. In addition pulse justification (pulse stuffing) time slots are provided, catering for the differences in phase and frequency between the individual tributary data and the main data stream, to control the remote oscillators in the demultiplexers. In the event of a data stream failure it is necessary to transmit an alarm indication signal over the failed data stream however the pulse justification equipment attempts to force the bit rate to zero. To overcome this, in the prior art, the data stream is replaced by one generated from a standby oscillator. Significant frequency deviations between the actual data stream when replaced and the injected data stream can be experienced causing substantial controlled oscillator realignment delays to be experienced even for short breaks. The proposal overcomes these problems by providing a shift register storage arrangement which is driven in parallel by the justification signals applied to the tributary data stream under normal operating conditions but does not have any output path. When the data stream fails the contents of the shift register are used to simulate the justification signals. Recirculation of the simulated justification signals also takes place while the data stream failure persists. The size of the simulated sequence (i.e. size of the shift register) determines the accuracy of the controlled oscillator and therefore the realignment delay.
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