发明名称 ERROR CORRECTING SYSTEM
摘要 PURPOSE:To realize the correction for the 2-bit error in a simple constitution, by storing the 1-bit error position into the error register and then actuating the 2nd error correcting circuit in case the error of 2-bits or more is diagnosed. CONSTITUTION:The parity redundant outputs read out of memory M are counted by syndrome calculator circuit SG and via the 2nd error correcting circuit DC'. And the 1-bit error position is stored in register EL via decoder DEC. When the calculation result of circuit SG is decided as the 2-bit error, the gate of register EL is opened via external device 2. And the inverse correction is given at circuit DC' to the bit position information which is designated by register EL of the rereading data of memory M. Accordingly, the rereading information corrected at circuit DC' is turned to the 1-bit error information substantially. Thus the correction is given through a simple constitution to the 2-bit error via circuit SG, decoder DEC and the 1st correcting circuit DC each.
申请公布号 JPS563498(A) 申请公布日期 1981.01.14
申请号 JP19790078725 申请日期 1979.06.22
申请人 FUJITSU LTD 发明人 TANIGUCHI SHIYOUZOU;IIJIMA KIYOKATSU;SAKURABA TAKAHIRO
分类号 G06F11/10;G06F12/16;G11C29/00 主分类号 G06F11/10
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