发明名称 INSPECTION UNIT FOR RANDOM LOGIC CIRCUIT
摘要 PURPOSE:To improve the efficiency of inspection greatly by supplying checked circuits with a common function-testing input pattern signal at a time after setting the initial values of all checked circuits in testing functions of the checked circuits. CONSTITUTION:To initialize checked circuits 3a-3d in terms of their internal logic states after the electric power source is put to work, clock pulses phia-phid from clock generating circuit 2 are input and by the monitor output, the application of the clock pulses is stopped via control circuit 5 in the order of detection 4a-4d of initialization. After the initial values of all tested circuits are set, the tested circuits can be operated synchronously and an input pattern signal for the function test is input from generating circuit 1 in common so as to input the decision result to fail register 7 via deciding circuits 6a-6d. The output of register 7 is compared with the contents of masking registers 8a-8d by gates Ga-Gd to obtain inspection results. The checked circuit can be tested in parallel, so that the inspection efficiency will be improved.
申请公布号 JPS562045(A) 申请公布日期 1981.01.10
申请号 JP19790076753 申请日期 1979.06.20
申请人 HITACHI LTD 发明人 NAKAMURA SADAO
分类号 G06F11/22;G01R31/28;G01R31/319 主分类号 G06F11/22
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