| 摘要 |
PURPOSE:To obtain an output control unit with less number of components and high reliability having compactness is total and low cost, by using integrated memory units. CONSTITUTION:The output of address lines 3a-3n output from a central logic operation unit 1 is converted at an address conversion unit 10, and the output of a designation signal 11a of a status memory unit 12a is at [H]. In this case, a data signal line 4 is at [H] level and the output of a timing signal line 5 is output from the operation unit 1 as leading pulse signal. The memory unit 20 outputs the memory status designated with address signal lines 3a-3n when the output of the timing signal line 5 is at [H]. Accordingly, an AND gate 23 of the status memory unit 12a delivers the output of [H] level with the input condition of [H] and FF19a is set. Then, output permission signal 6a of [H] is delivered and a corresponding unit among process unit group 9 is driven via a buffer unit 7 and an output signal line 8a. |
