发明名称 PHASE LOCKED LOOP SYNCHRONIZER
摘要 An AFPC loop for TV horizontal oscillator suitable for use with sync signals subject to timing instability includes means for maintaining a long response time during the equalizing and vertical sync intervals to reduce drift, and shortens the loop response time after the second equalizing pulse interval for maximum correction.
申请公布号 JPS55156478(A) 申请公布日期 1980.12.05
申请号 JP19800062160 申请日期 1980.05.09
申请人 RCA CORP 发明人 SUCHIIBUN ARAN SUTETSUKURA;ARUBIN RUUBEN BARABAN
分类号 H03L7/107;H04N5/05;H04N5/12 主分类号 H03L7/107
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