| 摘要 |
The device has n<-> type tape-like surface regions (14a,14b,14c) of determined lengths, which are up-to-surface extensions of n<-> type drift layer, the surface regions are surrounded by p-type well regions (13). The drift layer is formed on a resistive layer adjoining the drain electrode. The gate electrode is formed between the surface and source regions, and an insulating film is laid between the gate electrode and the semiconductor surface. The source electrode is formed above the gate electrodes, having an insulating film in contact with the source and wells region. The ratio of total areas of surface regions to well regions, which includes the source region, is in the range 0.01-0.2. The tape of the surface region is of width 0.1-2 micrometre in the main part, and the length is equal to or greater than 100 micrometre, or 500 micrometre. The tape of the surface region comprises a set of convex parts dividing the tape in a direction different from that of the extension, the convex part is up to 50 micrometre, or 250 micrometre, of the tape, and extends to 2 micrometre or less with respect to the surface region. The gate electrode is in the form of a set of tapes, each surrounded by the wells region in a plane parallel to the semiconductor surface. Each tape covers one or more surface regions, and the width is 4-8 micrometre, or 5-7 micrometre, and the length is equal to or greater than 100 micrometre, or 500 micrometre. The gate electrode comprises bridges connecting the tapes, of widths equal to or less than 4 micrometre, and the wells region extends below the main parts of the bridges. The drift layer comprises regions of different conductivity types laid out in alternation. The resistivity in parts of surface regions which are less deep than the wells region is below the resistivity in parts of the drift layer which is deeper than the wells region. The doping level of the surface regions is in the range 2 x 10<12> - 5 x 10<12>/sq.cm., or 2.5 x 10<12> - 4 x 10<12>/sq.cm. The device comprises the guard rings of p-type conductivity in the surface part of semiconductor surrounding the wells region. The number of guard rings is equal to or greater than n, which is calculated from the formula: n = 1.0 x Vbr/100, or n = 1.5 x Vbr/100, or n = 6.0 x Vbr/100, where Vbr is the breakdown voltage. The spacing between the wells region and the first guard ring is 1 micrometre or less, or 0.5 micrometre or less, or the first guard region is in contact with the wells region. The spacing between the first and second guard rings is 1.5 micrometre or less, or 1 micrometre or less, or 0.5 micrometre or less. The spacing between the second and the third guard rings is 2 micometre or less, or 0.5 micrometre or less. The spacing between the second and the third guard rings is 2 micrometre or less, or 1 micrometre or less. The spacing, between the third and the fourth guard rings is 2.5 micrometre or less, or 2 micrometre or less. The spacing between the wells region and the first guard ring is equal to d1/4 or less, where d1 is the depth smaller of the depth of junction of wells region and the junction of the guard ring, or is equal to d1/8 or less. The spacing between the first and the second guard rings is equal to d2/4 or less, where d2 is the depth of the junction of guard ring, or equal to d2/8 or less. The spacing between the second and the third guard rings is equal to d2/4 or less, or d2/8 or less. The number of guard rings is equal to or greater than 5, 6 or 7. The device comprises an electrically conducting film above the surface of the drift layer between the wells region and the first guard ring, and a polymeric film for protection.
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