发明名称 CLOCK SIGNAL SWITCHING SYSTEM
摘要 PURPOSE:To realize the highly reliable clock signal switching by performing the switching of the clock signal at the clock reception side with installation of the main clock monitor circuit plus the main and secondary clock switching circuits each. CONSTITUTION:Outputs 24 and 20 feature L and H each while the main clock signal is supplied to terminal 12 of monostable multivibrator 9 from main clock line 21. As control input 15 of three-state 13 turns to H, the clock signal supplied to input 16 from line 21 is supplied to clock output line 23 via output 25 of three- state 15. And the secondary clock signal of input 19 never emerges at output line 23 since three-state 14 features control input 18 of L. With no supply of the main clock signal from line 21, output 20 turns to L along with input 15 turned also to L. Thus output 25 is cut off from the clock output line. At the same time, input 18 features H since output 24 turns to H, and thus the secondary clock signal applied to input 19 is supplied to output line 23 from output 17.
申请公布号 JPS55151887(A) 申请公布日期 1980.11.26
申请号 JP19790059566 申请日期 1979.05.15
申请人 NIPPON ELECTRIC CO 发明人 ISHII JIYUNICHI
分类号 H04Q3/545;G06F1/04;H04L7/00 主分类号 H04Q3/545
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