| 摘要 |
PURPOSE:To obtain a C-MOS logic circuit decreasing the number of FET's, by using the bidirectionality of MOSFET. CONSTITUTION:When the both logic inputs A3, B3 receive the voltage of Vin= VH (where; VH is ''H'' level signal) at the same time, FETs 3, 4 are conductive, FETs 1, 2 are non-conductive, and the ''H'' level signal of VH-Vth (where; Vth is the threshold voltage of FET) is given to the output terminal X3. On the other hand, when the voltage of Vth=VL (where; VL is ''L'' level signal) is fed at least to one of the logic inputs A3, B3, since one of FETs 1, 2 is conductive, the ''L'' level signal of VL+Vth is given to the output terminal X3. |
