SHARED DIRECT MEMORY ACCESS CONTROLLER

摘要

SHARED DIRECT MEMORY ACCESS CONTROLLER A microprocessor system includes a microprocessor, a memory, and one or more direct memory access controllers, all connected to a common system bus which includes a system address bus and a system data bus. At least one of the direct memory access controllers is shared by a plurality of subsystem device controllers which may control peripheral devices having diverse characteristics. The microprocessor is limited in its instruction repertoire and may control peripheral devices only by means of an input and an output instruction. The shared direct memory access controller includes no circuitry which is specifically for controlling only a single type of peripheral device, the device dependent logic being located in subsystem device controllers. Data transfers may take place directly between the memory and, through the shared direct memory access controller, any selected one of the peripheral devices. In order to set up the actual data transfer, the microprocessor executes an Input instruction which addresses the status register in a selected subsystem device controller and returns this status to the microprocessor. Next, two Output instructions are executed to load a memory starting address into an address pointer counter in the shared direct memory access controller. Finally, an Output instruction is executed to address a control register in the selected subsystem device controller to load it with a command. After this last operation the actual data transfer takes place on a byte basis through the shared direct memory access controller between the memory and the selected subsystem device controller. The shared direct memory access controller includes an interrupt priority encoder and circuits responsive to an interrupt that is granted priority for placing the status and address of the interrupting subsystem device controller on the system bus. Circuits are included in the shared direct memory access controller for "handshaking" between it and the memory, and between it and the subsystem device controllers.