| 摘要 |
<p>PURPOSE:To enable to prevent mis-output without large scale and complicated processing, by providing the two systems using two memory circuits and two defection detecting circuits. CONSTITUTION:The unit consists of the memory circuits M, M' made of MOSFETs and defection detecting circuits 31, 32. If the circuit M has a failure of output line nonshort circuit, the information of 1 is given to the output lines A, A' of the circuits M, M' with the timing pulse phip, and if the voltage of FETi, FET'i is the threshold voltage V1, the storage circuit 21 and the stored information SHO, SHO' are respectively obtained at 1 or at 0, 1 with the control voltage Vc, the circuits 31, 31' are conductive or nonconductive and the information SH1, SH1' are obtained at 0. If FETi, FET'i are conductive with the defection detecting voltage VD, the information of 1 or 0 stored in FETi, FET'i is read out without error. Further, if the circuit M has the output line shortage, the information stored in FETi, FET'i is read out without error. Accordingly, even if one of the memory circuits M, M' has a defection but another has no defection, no error is output to the information at the output terminal 43.</p> |
