| 摘要 |
A vertical frequency deflection signal generator includes a comparator whose output is coupled to a capacitor the voltage across which constitutes the vertical deflection voltage. The capacitor is charged from a voltage source in the vertical trace interval and discharged when the comparator output switches to ground potential, i.e. when the voltage at the inverting input of the comparator is greater than the voltage at the direct input. To synchronize such a vertical deflection signal generator to vertical synchronization pulses derived from an incoming television signal, the vertical synchronization signals are applied to the base of a transistor whose emitter-collector circuit is connected to the comparator output through a resistor. Each received vertical synchronization signal therefore causes a slight decrease in the output voltage of the comparator and, because of a feedback resistor, a corresponding decrease at the direct input of the comparator. The circuit is so balanced that a vertical synchronization signal received near the end of the trace interval will cause an early switching of the comparator, while noise pulses received other than near the end of the trace interval will have no effect. |
