发明名称 FREQUENCY MULTISTAGE CONTROL CIRCUIT OF DIGITAL FREQUENCY CONTROL OSCILLATOR
摘要 PURPOSE:To make it possible to vary a frequency greatly in a short time by inputting a pulse signal, when its number is a fixed value less or greater than the period of a clock signal, to the lowest-order and highest-order parts of a U/D (up/ down) counter. CONSTITUTION:Counter 3 generates output 22 only when the frequency variation of regulator 20 exceeds a fixed value. When retriggerable MSMV (monostable multivibrator) 4 is stable, AND gate 5 is held at the normal step side by its output to supply pulse 25 to the lowest-order digit of U/D counter 12 controlling programmable counter 11. Next, when output 22 is generated, it serves as the trigger of MSMV4 to invert outputs 23 and 24 as long as the setting holding time of MSMV4, and gate 5 is switched to the fast winding step side to supply adjustment pulse 26 to the highest-order digit of counter 12; for example, when this is input to the digit right over 10Hz, a change of one-pulse 100Hz ia made and when to that two digits higher, the change of one-pulse 1KHz is made.
申请公布号 JPS55134543(A) 申请公布日期 1980.10.20
申请号 JP19790041758 申请日期 1979.04.06
申请人 YAESU MUSEN KK 发明人 SUZUKI MINORU;KURAKATA MINORU;FUJIKI SHIROU
分类号 H03L7/18;H03J5/02;H03K23/00;H03L7/16;H03L7/183 主分类号 H03L7/18
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