Cell layout for SRAM FinFET transistors

摘要

An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

主权项

1. An SRAM cell array comprising:
a plurality of SRAM cells, each SRAM cell comprising six FinFETs including two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors; wherein each PU transistor includes one active fin having a first fin width, the one active fin of each PU transistor being adjacent to each other; wherein each PG transistor shares at least one active fin with a PD transistor; wherein the at least one active fin shared by a PG transistor and a PD transistor has a second fin width smaller than the first fin width; and wherein no dummy fin is disposed between the one active fin of each PU transistor in a memory cell, a dummy fin is disposed between a PU transistor and the at least one active fin shared by a PG transistor and the PD transistor, and at least one dummy fin is disposed between the at least one active fin shared by the PG transistor and PD transistor in the memory cell and a fin shared by a PG transistor and a PD transistor in an adjacent memory cells.