发明名称 N-Bit magnitude comparator of free design
摘要 An N-bit magnitude comparator of tree design having a plurality of one-bit magnitude comparators connected to a cascading network with a first stage adapted to receive signals from each pair of the one-bit magnitude comparators and subsequent stages for receiving signals from the preceding stage in the cascade network. The first and every alternate stage thereafter in the cascading circuit comprises means for inverting the signal polarity to the input of that stage so as to achieve one gate delay per circuit.
申请公布号 US4225849(A) 申请公布日期 1980.09.30
申请号 US19780901412 申请日期 1978.05.01
申请人 FUJITSU LIMITED 发明人 LAI, HUNG C.
分类号 G06F7/02;(IPC1-7):G06F7/04 主分类号 G06F7/02
代理机构 代理人
主权项
地址