Primary PCM bit stream alignment - using extendable buffer store and bit stuffing to align primary PCM for secondary multiplexing

摘要

A phase comparator circuit aligns the bit streams of incoming 2.048 Mbit/s prim. systems for multiplexing to the higher order 8.448 Mbit/s. The incoming 2Mbit/s bit streams are counted into a buffer store at N and 2N the prim. bit rate so that the signal can be read out at the writing in rate of the sec. higher order system and the prim. 2 Mbit/s removed. Synchronisation and stuffing bits are also added as reqd. The incoming prim. 2 Mbit/s bit streams are each fed into an extendible buffer store. Each of the four incoming prim. bit streams has a separate store. The writing in pulse generator is supplied with a 2.048 Mbit/s input and delivers 2N so that the pulse width is able to store the incoming bit stream information even though no jitter and line distortions have occurred. Both the output pulse generator and the writing is pulse generator are synchronised to a data selector.