| 摘要 |
PURPOSE:To enable to permit even in timing for each request signal with the reset priority type flip flop and a simple control circuit. CONSTITUTION:The request signals REQ0...REQ7 are connected to the inputs RI0...RI7 of the request reception circuit 100 consisting of the reset priority type flip flop's and to the inputs a0...a7 of the control circuit 400, the outputs RO0...RO7 of request reception circuit 100 are connected to the inputs J0...J7 of the priority circuit 200, and the oututs X0...X7 are connected to the inputs AI0...AI7 of the ACK hold circuit 300 consisting of the reset priority type flip flop group. The output of the ACK hold circuit 300 is the request permission signals ACK0...ACK7 and connected to the inputs b0...b7 of the control circuit 400. The output c of the control circuit 400 is the timing signal T1 and connected to the set input terminals SR of the request reception circuit 100. Further, the output d of the control circuit 400 is the timing signal T2n and connected to the set input terminal SA of the ACK hold circuit 300. |
