| 摘要 |
PURPOSE:To reduce the capacity of a digit line and accelerate a response speed to reduce the power consumption of a semiconductor device by applying a bias voltage only to a special island region. CONSTITUTION:A P<+>-type region is formed in a P-type well formed in an N-type substrate for a complementary insulated gate semiconductor device, and connected to an electrode W. When memory cells are selected, a selection signal SEL activates in advance to the selection a potential generator VG to apply a potential zero volt or loss to the P-type well. Then, it applies positive potential to the line or row to operate an address transistor. Thus, it can improve the delay in response speed due to the capacity of the digit line and reduce the power consumption. |
