发明名称 DIGITAL SIGNAL DELAY UNIT
摘要 PURPOSE:To suppress the production of noise with a simple constitution, by holding and outputting the digital signal read out from RAM for a given time relating to the values before and after the set value and the sampling frequency, when the detected output of the comparison circuit is present. CONSTITUTION:Digital signal is fed to RAM2 and the signal delayed by desired period is outputted with RAM2. In this case, the preset circuit 7 counts the signal in frequency equal to the sampling frequency and the count start value if the counter 4 fed to RAM2 is set to desired value. Further, the comparison circuit 14 detects the output set value of the circuit 7 when it is altered to smaller value than the previous value. The digital signal read out from RAM2 is passed through as it is when no detection output is present, and if the detection output is present, the signal is held 15 and outputted for a given time relating to the difference before and after the set value and to the sampling frequency. Thus, with a comparatively simple circuit constitution, the production of noise due to rapid change in the signal level can be suppressed.
申请公布号 JPS55110414(A) 申请公布日期 1980.08.25
申请号 JP19790018232 申请日期 1979.02.19
申请人 VICTOR COMPANY OF JAPAN 发明人 MATSUSHIGE TAKASHI;KASUGA MASAO;SATOU MASAAKI
分类号 H03H11/26;H03H17/00 主分类号 H03H11/26
代理机构 代理人
主权项
地址