| 摘要 |
A high frequency divider arrangement for use in transmission systems operating in the gigabit/second range. Known divider arrangements based on ECL logic families have an upper frequency limit which is too low for dividing signals in the gigabit/second range. In one embodiment the inputs of a high frequency multiplexer are connected respectively to the stages of a feedback shift register which produces a sequence of five code words which are serialized by a multiplexer. The bits in the serialized code words occur in blocks which define a mark/space ratio of the output signal which has a frequency of 2/5ths of the clock frequency applied to the multiplexer. By means of additional circuitry, for example D-type flip-flops, the output from the multiplexer can be divided further. The code word(s) applied to the multiplexer can be held static, changed each time the inputs of the multiplexer have been scanned, or held temporarily static for a predetermined number of scans and then changed. |
